HD64F2168 Datasheet, PDF (590/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
1 CTLWI 0
R/(W)*  Control Code Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the control code to SMICCSR.
When the IBFIE3 bit and CTLWIE bit are set to1, the
IBFI3 interrupt is requested to the slave.
0: Control code transmission wait state
[Clearing condition]
After the slave reads CTLWI = 1, writes 0 to this bit.
1: Control code transmission end
[Setting condition]
When the host writes the status code to SMICCSR.
0 BUSYI
R/(W)*  Transfer Start Interrupt
This is a status flag that indicates that the host starts
transferring. When the IBFIE3 bit and BUSYIE bit
are set to 1, the IBFI3 interrupt is requested to the
slave.
0: Transfer start wait state
[Clearing condition]
After the slave reads BUSYI = 1, writes 0 to this bit.
1: Transfer start
[Setting condition]
When the rising edge of the BUSY bit in SMICFLG is
detected.
Note: * Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 550 of 830