HD64F2168 Datasheet, PDF (195/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 7.1 Correspondence between Interrupt Sources and DTCER
Register
Bit Bit Name DTCERA
DTCERB
DTCERC
7 DTCEn7 (16)IRQ0
(53)OCIB
(69)CMIB1
6 DTCEn6 (17)IRQ1
(76)IICI2
(72)CMIAY
5 DTCEn5 (18)IRQ2
(94)IICI0
(73)CMIBY
4 DTCEn4 (19)IRQ3

(29)EVENTI
3 DTCEn3 (28)ADI

(44)CMIAX
2 DTCEn2 (48)ICIA
(64)CMIA0 (81)RXI0
1 DTCEn1 (49)ICIB
(65)CMIB0 (82)TXI0
0 DTCEn0 (52)OCIA
(68)CMIA1 (85)RXI1
[Legend]
n:
A to E
( ): Vector number
: Reserved. The write value should always be 0.
DTCERD
(86)TXI1
(89)RXI2
(90)TXI2
(78)IICI3
(98)IICI1


(45)CMIBX
DTCERE




(104)ERR1
(105)IBFI1
(106)IBFI2
(107)IBFI3
7.2.8 DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Initial
Bit
Bit Name Value
7
SWDTE 0
R/W Description
R/W DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be written
to this bit.
[Clearing conditions]
• When the DISEL bit is 0 and the specified number
of transfers have not ended
• When 0 is written to the DISEL bit after a software-
activated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
This bit will not be cleared when the DISEL bit is 1 and
data transfer has ended or when the specified number
of transfers has ended.
Rev. 3.00, 03/04, page 155 of 830