HD64F2168 Datasheet, PDF (525/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.4.6 Slave Transmit Operation
If the slave address matches to the address in the first frame (address reception frame) following
the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is
automatically set to 1 and the mode changes to slave transmit mode.
Figure 15.23 shows the sample flowchart for the operations in slave transmit mode.
Slave transmit mode
Clear IRIC in ICCR
Write transmit data in ICDR
Clear IRIC in ICCR
[1], [2] If the slave address matches to the address in the first frame
following the start condition detection and the R/W bit is 1
in slave receive mode, the mode changes to slave transmit mode.
[3], [5] Set transmit data for the second and subsequent bytes.
Read IRIC in ICCR
No
IRIC = 1?
Yes
Read ACKB in ICSR
No
End
of transmission
(ACKB = 1)?
Yes
Clear IRIC in ICCR
Clear ACKE to 0 in ICCR
(ACKB=0 clear)
Set TRS = 0 in ICCR
Read ICDR
[3], [4] Wait for 1 byte to be transmitted.
[4] Determine end of transfer.
[6] Clear IRIC in ICCR
[7] Clear acknowledge bit data
[8] Set slave receive mode.
[9] Dummy read (to release the SCL line).
Read IRIC in ICCR
No
IRIC = 1?
Yes
Clear IRIC in ICCR
End
[10] Wait for stop condition
Figure 15.23 Sample Flowchart for Slave Transmit Mode
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
Rev. 3.00, 03/04, page 485 of 830