HD64F2168 Datasheet, PDF (30/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figure 14.47 MSB-First Data Transmission............................................................................... 430
Figure 14.48 LSB-First Data Reception ..................................................................................... 431
Figure 14.49 MSB-First Data Reception .................................................................................... 432
Figure 14.50 LSB-First and MSB-First Transmit Data .............................................................. 433
Section 15 I²C Bus Interface (IIC)
Figure 15.1 Block Diagram of I²C Bus Interface ....................................................................... 436
Figure 15.2 I²C Bus Interface Connections (Example: This LSI as Master) .............................. 437
Figure 15.3 I²C Bus Data Formats (I²C Bus Formats)................................................................ 465
Figure 15.4 I²C Bus Data Formats (Serial Formats)................................................................... 465
Figure 15.5 I²C Bus Timing........................................................................................................ 466
Figure 15.6 Sample Flowchart for IIC Initialization .................................................................. 467
Figure 15.7 Sample Flowchart for Operations in Master Transmit Mode .................................. 468
Figure 15.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)........... 470
Figure 15.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0) ................................................................................................. 470
Figure 15.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............. 471
Figure 15.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1)............................................................................. 473
Figure 15.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)............................................................................. 473
Figure 15.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1) .................................................................. 474
Figure 15.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1) .................................................................... 475
Figure 15.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 477
Figure 15.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 478
Figure 15.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 479
Figure 15.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)....... 481
Figure 15.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)....... 481
Figure 15.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 482
Figure 15.21 Slave Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, HNDS = 0)............................................................................ 484
Figure 15.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0)............................................................................ 484
Figure 15.23 Sample Flowchart for Slave Transmit Mode......................................................... 485
Figure 15.24 Slave Transmit Mode Operation Timing Example (MLS = 0).............................. 487
Figure 15.25 IRIC Setting Timing and SCL Control (1) ............................................................ 488
Figure 15.26 IRIC Setting Timing and SCL Control (2) ............................................................ 489
Figure 15.27 IRIC Setting Timing and SCL Control (3) ............................................................ 490
Figure 15.28 Block Diagram of Noise Canceler......................................................................... 492
Rev. 3.00, 03/04, page xxx of xl