HD64F2168 Datasheet, PDF (22/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

20.5.1 Hardware Protection ............................................................................................ 665
20.5.2 Software Protection ............................................................................................. 666
20.5.3 Error Protection ................................................................................................... 666
20.6 Switching between User MAT and User Boot MAT........................................................ 668
20.7 Programmer Mode ............................................................................................................ 669
20.8 Serial Communication Interface Specification for Boot Mode......................................... 670
20.9 Usage Notes ...................................................................................................................... 695
Section 21 Boundary Scan (JTAG) ................................................................... 697
21.1 Features............................................................................................................................. 697
21.2 Input/Output Pins.............................................................................................................. 699
21.3 Register Descriptions........................................................................................................ 700
21.3.1 Instruction Register (SDIR) ................................................................................. 701
21.3.2 Bypass Register (SDBPR) ................................................................................... 703
21.3.3 Boundary Scan Register (SDBSR) ...................................................................... 703
21.3.4 ID Code Register (SDIDR).................................................................................. 713
21.4 Operation .......................................................................................................................... 714
21.4.1 TAP Controller State Transitions......................................................................... 714
21.4.2 JTAG Reset.......................................................................................................... 715
21.5 Boundary Scan.................................................................................................................. 715
21.5.1 Supported Instructions ......................................................................................... 715
21.6 Usage Notes ...................................................................................................................... 718
Section 22 Clock Pulse Generator..................................................................... 721
22.1 Oscillator........................................................................................................................... 722
22.1.1 Connecting Crystal Resonator ............................................................................. 722
22.1.2 External Clock Input Method .............................................................................. 723
22.2 PLL Multiplier Circuit ...................................................................................................... 724
22.3 Medium-Speed Clock Divider .......................................................................................... 724
22.4 Bus Master Clock Select Circuit....................................................................................... 724
22.5 Subclock Input Circuit ...................................................................................................... 724
22.6 Subclock Waveform Forming Circuit............................................................................... 724
22.7 Clock Select Circuit .......................................................................................................... 725
22.8 Usage Notes ...................................................................................................................... 725
22.8.1 Note on Resonator ............................................................................................... 725
22.8.2 Notes on Board Design ........................................................................................ 725
22.8.3 Note on Operation Check .................................................................................... 726
Section 23 Power-Down Modes........................................................................ 727
23.1 Register Descriptions........................................................................................................ 728
23.1.1 Standby Control Register (SBYCR) .................................................................... 728
23.1.2 Low-Power Control Register (LPWRCR) ........................................................... 730
Rev. 3.00, 03/04, page xxii of xl