HD64F2168 Datasheet, PDF (559/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
4 ABRT 0
R/(W)*  LPC Abort Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
a forced termination (abort) of an LPC transfer cycle
occurs.
0: [Clearing conditions]
• Writing 0 after reading ABRT = 1
• LPC hardware reset
• LPC software reset
• LPC hardware shutdown
• LPC software shutdown
1: [Setting condition]
• LFRAME pin falling edge detection during LPC
transfer cycle
3 IBFIE3 0
R/W  IBFI3 Interrupt Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
completed interrupt requests and SMIC mode and
BT mode interrupt requests are disabled
1: [When TWRE in LADR3 = 0]
Input data register IDR3 receive completed
interrupt request and SMIC mode and BT mode
interrupt requests are enabled
[When TWRE in LADR3 = 1]
Input data register IDR3 and TWR receive
completed interrupt requests and SMIC mode and
BT mode interrupt requests are enabled
2 IBFIE2 0
R/W  IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register IDR2 receive completed
interrupt requests disabled
1: Input data register IDR2 receive completed
interrupt requests enabled
Rev. 3.00, 03/04, page 519 of 830