HD64F2168 Datasheet, PDF (849/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

LCLK
t_LCKH
t_Lcyc
LCLK
t_LCKL
LAD3 to LAD0,
SERIRQ, CLKRUN
(Transmit signal)
LAD3 to LAD0,
SERIRQ, CLKRUN,
LFRAME
(Receive signal)
LAD3 to LAD0,
SERIRQ, CLKRUN
(Transmit signal)
t_TXD
t_RXS
t_RXH
t_OFF
Figure 25.31 LPC Interface (LPC) Timing
Table 25.13 JTAG Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item
ETCK clock cycle time
ETCK clock high pulse width
ETCK clock low pulse width
ETCK clock rise time
ETCK clock fall time
ETRST pulse width
Reset hold transition pulse width
ETMS setup time
ETMS hold time
ETDI setup time
ETDI hold time
ETDO data delay time
Note: * When t_cyc ≤ t_TCKcyc
Symbol Min.
t_TCKcyc
t
TCKH
t
TCKL
t_TCKr
t_TCKf
t_TRSTW
t_RSTHW
t
TMSS
t
TMSH
t
TDIS
t
TDIH
t
TDOD
40*
15
15


20
3
20
20
20
20

Max.
200*


5
5






20
Unit
ns
t_cyc
ns
Test Conditions
Figure 25.32
Figure 25.33
Figure 25.34
Rev. 3.00, 03/04, page 809 of 830