HD64F2168 Datasheet, PDF (770/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 23.1 Operating Frequency and Wait Time
STS2 STS1 STS0 Wait Time
0 0 0 8192 states
0 0 1 16384 states
0 1 0 32768 states
0 1 1 65536 states
1 0 0 131072 states
1 0 1 262144 states
1 1 0 Reserved
1 1 1 16 states*
Recommended specification
Note: Setting prohibited.
33M Hz 25M Hz 20 MHz 10 MHz 8 MHz 6 MHz Unit
0.2
0.3
0.4
0.8
1.0
1.3
ms
0.5
0.7
0.8
1.6
2.0
2.7
1.0
1.3
1.6
3.3
4.1
5.5
2.0
2.6
3.3
6.6
8.2
10.9
4.0
5.2
6.6
13.1 16.4 21.8
8.0
10.5 13.1 26.2 32.8 43.7






0.5
0.7
0.8
1.6
2.0
2.7
µs
23.1.2 Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes and signals in the multiplex bus extended mode.
Initial
Bit Bit Name Value R/W Description
7
DTON
0
R/W Direct Transfer On Flag
Specifies the operating mode to be entered after executing the
SLEEP instruction.
When the SLEEP instruction is executed in high-speed mode or
medium-speed mode:
0: Shifts to sleep mode, software standby mode, or watch mode
1: Shifts directly to subactive mode, or shifts to sleep mode or
software standby mode
When the SLEEP instruction is executed in subactive mode:
0: Shifts to subsleep mode or watch mode
1: Shifts directly to high-speed mode, or shifts to subsleep mode
Rev. 3.00, 03/04, page 730 of 830