HD64F2168 Datasheet, PDF (167/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

6.5.3 Basic Operation Timing in Normal Extended Mode
(1) 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access
space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
Wait states cannot be inserted.
Bus cycle
T₁
T₂
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS* (IOSE = 0)
RD
Read D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
D15 to D8
Valid
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space
Rev. 3.00, 03/04, page 127 of 830