HD64F2168 Datasheet, PDF (187/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

6.7 Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (T_I) between
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
If an external write occurs after an external read while the ICIS bit is set to 1 in BCR, an idle cycle
is inserted at the start of the write cycle.
Figure 6.29 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.29 (a),
with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.29 (b), an idle cycle is inserted, thus preventing data collision.
φ
Address bus
RD
WR
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
RD
WR
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Data bus
Data bus
Data collision
Long output floating time
(a) No idle cycle insertion
(b) Idle cycle insertion
Figure 6.29 Examples of Idle Cycle Operation
Table 6.17 shows the pin states in an idle cycle.
Table 6.17 Pin States in Idle Cycle
Pins
A23 to A0
D15 to D0
AS, IOS, CS256, CPCS1
RD
HWR, LWR
Pin State
Contents of immediately following bus cycle
High impedance
High
High
High
Rev. 3.00, 03/04, page 147 of 830