HD64F2168 Datasheet, PDF (330/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

11.5 Operation Timing
11.5.1 FRC Increment Timing
Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the
increment timing with an external clock source. The pulse width of the external clock signal must
be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is
shorter than 1.5 system clocks (φ).
φ
Internal clock
FRC input
clock
FRC
N–1
N
N+1
Figure 11.3 Increment Timing with Internal Clock Source
φ
External clock
input pin
FRC input
clock
FRC
N
N+1
Figure 11.4 Increment Timing with External Clock Source
Rev. 3.00, 03/04, page 290 of 830