HD64F2168 Datasheet, PDF (622/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 16.10 Serial Interrupt Transfer Cycle Frame Configuration
Frame
Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Serial Interrupt Transfer Cycle
Contents
Drive
Source
Number
of States
Start
Slave
6
Host
IRQ0
Slave
3
IRQ1
Slave
3
SMI
Slave
3
IRQ3
Slave
3
IRQ4
Slave
3
IRQ5
Slave
3
IRQ6
Slave
3
IRQ7
Slave
3
IRQ8
Slave
3
IRQ9
Slave
3
IRQ10
Slave
3
IRQ11
Slave
3
IRQ12
Slave
3
IRQ13
Slave
3
IRQ14
Slave
3
IRQ15
Slave
3
IOCHCK
Slave
3
Stop
Host
Undefined
Notes
In quiet mode only, slave drive possible in first
state, then next 3 states 0-driven by host
Drive possible in LPC channel 1
Drive possible in LPC channels 2 and 3
Drive possible in LPC channels 2 and 3
Drive possible in LPC channels 2 and 3
Drive possible in LPC channels 2 and 3
Drive possible in LPC channels 2 and 3
Drive possible in LPC channel 1
First, 1 or more idle states, then 2 or 3 states
0-driven by host
2 states: Quiet mode next
3 states: Continuous mode next
There are two modescontinuous mode and quiet modefor serialized interrupts. The mode
initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer
cycle that ended before that cycle.
In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet
mode, the slave processor with interrupt sources requiring a request can also initiate an interrupt
transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate
interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-
down state. In order for a slave to transfer an interrupt request in this case, a request to restart the
Rev. 3.00, 03/04, page 582 of 830