HD64F2168 Datasheet, PDF (662/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

• Flash Code Control Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence
during programming or erasing flash memory and the download of on-chip program.
Initial
Bit
Bit Name Value R/W Description
7
FWE
1/0
R
Flash Program Enable
Monitors the signal level input to the FWE pin and
enables or disables programming/erasing flash memory.
0: Programming/erasing disabled
1: Programming/erasing enabled
6, 5 
All 0
R/W Reserved
The initial value should not be changed.
4
FLER 0
R
Flash Memory Error
Indicates an error occurs during programming and
erasing flash memory. When FLER is set to 1, flash
memory enters the error protection state.
When FLER is set to 1, high voltage is applied to the
internal flash memory. To reduce the damage to flash
memory, the reset must be released after the reset
period of 100 µs which is longer than normal.
0: Flash memory operates normally.
Programming/erasing protection for flash memory
(error protection) is invalid.
[Clearing condition]
• At a reset or in hardware standby mode
1: An error occurs during programming/erasing flash
memory.
Programming/erasing protection for flash memory
(error protection) is valid.
[Setting conditions]
• When an interrupt, such as NMI, occurs during
programming/erasing flash memory.
• When the flash memory is read during
programming/erasing flash memory (including a
vector read or an instruction fetch).
• When the SLEEP instruction is executed during
programming/erasing flash memory (including
software-standby mode)
• When a bus master other than the CPU, such as the
DTC, gets bus mastership during
programming/erasing flash memory.
Rev. 3.00, 03/04, page 622 of 830