HD64F2168 Datasheet, PDF (349/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

12.3 Register Descriptions
The TMR has the following registers for each channel. For details on the serial timer control
register, see section 3.2.3, Serial Timer Control Register (STCR).
• Timer counter (TCNT)
• Time constant register A (TCORA)
• Time constant register B (TCORB)
• Timer control register (TCR)
• Timer control/status register (TCSR)
• Input capture register (TICR)*¹
• Time constant register C (TCORC)*¹
• Input capture register R (TICRR)*¹
• Input capture register F (TICRF)*¹
• Timer input select register (TISR)*²
• Timer connection register I (TCONRI)*¹
• Timer connection register S (TCONRS)*¹
Notes: Some of the registers of TMR_X and TMR_Y use the same address. The registers can
be switched by the TMRX/Y bit in TCONRS.
1. Only for the TMR_X
2. Only for the TMR_Y
12.3.1 Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-
bit register, so they can be accessed together by word access. The clock source is selected by the
CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare-
match A signal or compare-match B signal. The method of clearing can be selected by the CCLR1
and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in
TCSR is set to 1. TCNT is initialized to H'00.
TCNT_Y can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 1. TCNT_X can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y
bit in TCONRS is 0. See section 3.2.2, System Control Register (SYSCR), and section 12.3.11,
Timer Connection Register S (TCONRS).
Rev. 3.00, 03/04, page 309 of 830