HD64F2168 Datasheet, PDF (605/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
1 B2H_IRQ 0
R/(W)*¹ R/(W)*³ BMC to HOST interrupt
Informs the host that an interrupt has been
requested when the BEVT_ATN or B2H_ATN bit
has been set. The SERIRQ is not issued. To
generate the SERIRQ, it should be issued by the
program.
0: B2H_IRQ interrupt is not requested
[Clearing condition]
When the host writes a 1.
1: B2H_IRQ interrupt is requested
[Setting condition]
When the slave writes a 1, after a 0 has been
read from B2H_IRQ
0 B2H_IRQ_ 0
EN
R
R/W BMC to HOST interrupt enable
Enables or disables the B2H_IRQ interrupt which
is an the interrupt source from the slave to the
host.
0: B2H_IRQ interrupt is disabled
[Clearing condition]
When a 0 is written by the host.
1: B2H_IRQ interrupt is enabled
[Setting condition]
When a 1 is written by the host.
Notes: 1. Only 1 can be written to set this flag.
2. Only 0 can be written to clear this flag.
3. Only 1 can be written to clear this flag.
4. Only 0 can be written to set this flag.
Rev. 3.00, 03/04, page 565 of 830