HD64F2168 Datasheet, PDF (689/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

(3) Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 20.12.
Start erasing procedure
program
Select on-chip program
to be downloaded and
specify download
destination by FTDAR
1.
Set FKEY to H'A5
Set SCO to 1 and
execute download
Clear FKEY to 0
DPFR = 0?
Yes
No
Download error processing
Set the FPEFEQ
parameter
Initialization
JSR FTDAR setting + 32
FPFR = 0 ?
No
Yes _{Initialization error processing}
1
1
Disable interrupts and
bus master operation
other than CPU
Set FKEY to H'5A
Set FEBS parameter
2.
Erasing
JSR FTDAR setting + 16
3.
FPFR = 0 ?
Yes
4.
No
Clear FKEY and erasing
error processing
No
Required block
erasing is
completed?
5.
Yes
Clear FKEY to 0
6.
End erasing
procedure program
Figure 20.12 Erasing Procedure
The procedure program must be executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the
on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
For the downloaded on-chip program area, refer to the RAM map for programming/erasing in
figure 20.10.
A single divided block is erased by one erasing processing. For block divisions, refer to figure
20.4. To erase two or more blocks, update the erase block number and perform the erasing
processing for each block.
Rev. 3.00, 03/04, page 649 of 830