HD64F2168 Datasheet, PDF (611/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Slave
Host
Bit that indicates slave is ready for read transfer.
Issues when slave is ready for the next read transfer.
Slave waits for the BUSY bit in SMICFLG is set. _A
Wait for BUSY = 0
Host confirms the BUSY bit in SMICFLG.
The bit indicates slave (this LSI) is ready for receiving a new control code.
When BUSY = 1, access from host is disabled.
Waits for
RX_DATA_RDY = 1
Host confirms the RX_DATA_RDY bit in SMICFLG.
Write control code Host writes the Read control code to SMICCSR.
Slave confirms that control code is written to SMICCSR
by host.
The CTLWI bit in SMICIR0 is set.
Generate slave
interrupt
BUSY = 1
Host sets the BUSY bit in SMICFLG.
Slave confirms the rising edge of the BUSY bit in SMICFLG.
The BUSYI bit in SMICIR0 is set.
Generate slave
interrupt
Slave clears the RX_DATA_RDY bit in SMICFLG.
RX_DATA_RDY = 0
Slave reads the control code in SMICCSR.
Read control code
Slave writes transfer data to SMICDTR according to
Read control code.
Slave writes the status code to SMICCSR to notify the
processing completion status.
Slave clears the BUSY bit in SMICFLG to indicate transfer
completion.
Write transfer data
Write status code
BUSY = 0
Generate host
interrupt
Host confirms the falling edge of the BUSY bit in SMICFLG.
An interrupt is generated.
Read transfer data Host reads transfer data in SMICDTR.
Slave confirms that valid data is read from SMICDTR
by host.
The HDTRI bit in SMICIR0 is set.
Abnormal
A
Generate slave
interrupt
Read status code
Slave confirms that status code is read from SMICCSR
by host.
The STARI bit in SMICIR0 is set.
Normal
Generate slave
interrupt
Host confirms the status code in SMICCSR.
In the case of normal completion, the status code is reflected to the next step.
In the case of abnormal completion, the status code is READY and an error
is kept.
Figure 16.5 SMIC Read Transfer Flow
Rev. 3.00, 03/04, page 571 of 830