HD64F2168 Datasheet, PDF (152/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

6.4 Bus Control
6.4.1 Bus Specifications
The external address space bus specifications consist of three elements: bus width, the number of
access states, and the wait mode and the number of program wait states. The bus width and the
number of access states for on-chip memory and internal I/O registers are fixed, and are not
affected by the bus controller settings.
(1) In Normal Extended Mode
(a) Bus Width: A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in
WSCR, and the ABWCP bit in BCR2.
(b) Number of Access States: Two or three access states can be selected via the AST and
AST256 bits in WSCR, and the ASTCP bit in BCR2. When the 2-state access space is designated,
wait-state insertion is disabled.
In the burst ROM interface, the number of access states for the basic extended area is determined
regardless of the AST bit setting.
(c) Wait Mode and Number of Program Wait States: When the basic extended area is specified
as a 3-state access space by the AST bit in WSCR, the wait mode and the number of program wait
states to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in
WSCR. From 0 to 3 program wait states can be selected.
When the 256-kbyte extended area is specified as a 3-state access space by the AST256 bit in
WSCR, the wait mode and the number of program wait states to be inserted automatically is
selected by the WMS10, WC11, and WC10 bits in WSCR2. From 0 to 3 program wait states can
be selected.
When the CP extended area is specified as a 3-state access space by the ASTCP bit in BCR2, the
wait mode and the number of program wait states to be inserted automatically is selected by the
WMS21, WMS20, WC21, and WC20 bits in WSCR2. From 0 to 3 program wait states can be
selected.
The wait function for external extension is effective for connecting low-speed devices to the
external address space. However, this wait function may cause some problems when the operation
of bus masters other than the CPU, such as the DTC are to be delayed.
Tables 6.2 to 6.6 show each bit setting and external address space division in the address ranges of
the external address space, and the bus specifications for the basic bus interface of each area.
Rev. 3.00, 03/04, page 112 of 830