HD64F2168 Datasheet, PDF (529/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

When WAIT = 1, and FS = 0 or FSX = 0 (I²C bus format, wait inserted)
SCL
8
9
1
2
3
SDA
8
A
1
2
3
IRIC
User processing
Clear IRIC
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
8
9
1
SDA
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 15.26 IRIC Setting Timing and SCL Control (2)
Clear IRIC
Rev. 3.00, 03/04, page 489 of 830