HD64F2168 Datasheet, PDF (364/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

φ
TCNT
N
N+1
TCOR
N
Compare-match
signal
CMF
Figure 12.6 Timing of CMF Setting at Compare-Match
12.5.3 Timing of Timer Output at Compare-Match
When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0
bits in TCSR. Figure 12.7 shows the timing of timer output when the output is set to toggle by a
compare-match A signal.
φ
Compare-match A
signal
Timer output pin
Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal
12.5.4 Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 12.8 shows the timing of clearing the counter by a
compare-match.
φ
Compare-match
signal
TCNT
N
H'00
Figure 12.8 Timing of Counter Clear by Compare-Match
Rev. 3.00, 03/04, page 324 of 830