HD64F2168 Datasheet, PDF (139/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

5.7 Usage Notes
5.7.1 Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an
instruction such as BCLR or MOV, and if an interrupt is generated during execution of the
instruction, the interrupt concerned will still be enabled on completion of the instruction, so
interrupt exception handling for that interrupt will be executed on completion of the instruction.
However, if there is an interrupt request of higher priority than that interrupt, interrupt exception
handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be
ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.10
shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0.
The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the
interrupt is masked.
φ
Internal
address bus
Internal
write signal
TCR write cycle
by CPU
TCR address
CMIA exception handling
CMIEA
CMFA
CMIA
interrupt signal
Figure 5.10 Conflict between Interrupt Generation and Disabling
Rev. 3.00, 03/04, page 99 of 830