HD64F2168 Datasheet, PDF (378/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

WOVI0
(Interrupt request signal)
Internal NMI
(Interrupt request signal*²)
RESO signal*¹
Internal reset signal*¹
Interrupt
control
Reset
control
Overflow
Clock
Clock
selection
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
TCNT_0
TCSR_0
Module bus
WDT_0
Bus
interface
WOVI1
(Interrupt request signal)
Internal NMI
(Interrupt request signal*²)
RESO signal*¹
Internal reset signal*¹
Interrupt
control
Reset
control
Overflow
Clock
Clock
selection
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Internal clock
TCNT_1
TCSR_1
Module bus
Bus
interface
[Legend]
TCSR_0: Timer control/status register_0
TCNT_0: Timer counter_0
TCSR_1: Timer control/status register_1
TCNT_1: Timer counter_1
WDT_1
Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is
generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal
first resets the WDT in which the overflow has occurred first.
2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1.
The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from
that from WDT_1.
Figure 13.1 Block Diagram of WDT
Rev. 3.00, 03/04, page 338 of 830