HD64F2168 Datasheet, PDF (769/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value R/W
6 STS2
0
R/W
5 STS1
0
R/W
4 STS0
0
R/W
3 DTSPEED 0
R/W
2 SCK2 0
R/W
1 SCK1 0
R/W
0 SCK0 0
R/W
[Legend]
*:
Don't care
Description
Standby Timer Select 2 to 0
Select the wait time for clock settling from clock oscillation
start when canceling software standby mode, watch mode,
or subactive mode. Select a wait time of 8 ms (oscillation
settling time) or more, depending on the operating
frequency.
With an external clock, select a wait time of 500 µs
(external clock output settling delay time) or more,
depending on the operating frequency.
Table 23.1 shows the relationship between the STS2 to
STS0 values and wait time.
DTC Speed
Specifies the operating clock for the bus masters (DTC)
other than the CPU in medium-speed mode.
0: All bus masters operate based on the medium-speed
clock.
1: The DTC operates based on the system clock.
The operating clock is changed when a DTC transfer is
requested even if the CPU operates based on the medium-
speed clock.
System Clock Select 2 to 0
Select a clock for the bus master in high-speed mode or
medium-speed mode.
When making a transition to subactive mode or watch
mode, SCK2 to SCK0 must be cleared to 0.
000: High-speed mode (Initial value)
001: Medium-speed clock: φ/2
010: Medium-speed clock: φ/4
011: Medium-speed clock: φ/8
100: Medium-speed clock: φ/16
101: Medium-speed clock: φ/32
11*: Must not be set.
Rev. 3.00, 03/04, page 729 of 830