HD64F2168 Datasheet, PDF (211/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

φ
DTC activation
request
DTC request
Address
Vector read
Data transfer
Read Write Read Write
Transfer information
read
Transfer information
write
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
φ
DTC activation
request
DTC request
Address
Vector read
Data transfer
Read Write
Data transfer
Read Write
Transfer information
read
Transfer
information
write
Transfer
information
read
Transfer information
write
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
7.6.7 Number of DTC Execution States
Table 7.8 lists the execution status for a single DTC data transfer, and table 7.9 shows the number
of states required for each execution status.
Table 7.8 DTC Execution Status
Mode
Register
Information
Vector Read Read/Write
I
J
Normal
1
6
Repeat
1
6
Block transfer 1
6
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Data Read
K
1
1
N
Data Write
L
1
1
N
Internal
Operations
M
3
3
3
Rev. 3.00, 03/04, page 171 of 830