HD64F2168 Datasheet, PDF (370/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

12.9 Usage Notes
12.9.1 Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T₂ state of a TCNT write cycle as shown in
figure 12.13, the counter clear takes priority and the write is not performed.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 12.13 Conflict between TCNT Write and Counter Clear
Rev. 3.00, 03/04, page 330 of 830