|
HD64F2168 Datasheet, PDF (80/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer | |||
|
◁ |
Table 2.9 System Control Instructions
Instruction Size*
Function
TRAPA
â
Starts trap-instruction exception handling.
RTE
â
Returns from an exception-handling routine.
SLEEP
â
Causes a transition to a power-down state.
LDC
B/W
(EAs) â CCR, (EAs) â EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper eight bits are
valid.
STC
B/W
CCR â (EAd), EXR â (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper eight
bits are valid.
ANDC
B
CCR ⧠#IMM â CCR, EXR ⧠#IMM â EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ⨠#IMM â CCR, EXR ⨠#IMM â EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR â #IMM â CCR, EXR â #IMM â EXR
Logically exclusive-ORs the CCR or EXR contents with immediate data.
NOP
â
PC + 2 â PC
Only increments the program counter.
[Legend]
*:
Size refers to the operand size.
B:
Byte
W: Word
Rev. 3.00, 03/04, page 40 of 830
|
▷ |