HD64F2168 Datasheet, PDF (331/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

11.5.2 Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). When a compare-match signal occurs, the level
selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure
11.5 shows the timing of this operation for compare-match A.
φ
FRC
OCRA
N
N+1
N
N
N+1
N
Compare-match
A signal
OLVLA
Clear*
Output compare A
output pin FTOA
Note : * Indicates instruction execution by software.
Figure 11.5 Timing of Output Compare A Output
11.5.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
φ
Compare-match
A signal
FRC
N
H'0000
Figure 11.6 Clearing of FRC by Compare-Match A Signal
Rev. 3.00, 03/04, page 291 of 830