HD64F2168 Datasheet, PDF (25/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 2
Figure 1.2 Pin Arrangement (TFP-144).......................................................................................... 3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 19
Figure 2.2 Stack Structure in Normal Mode ................................................................................. 19
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 20
Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 21
Figure 2.5 Memory Map............................................................................................................... 22
Figure 2.6 CPU Internal Registers ................................................................................................ 23
Figure 2.7 Usage of General Registers ......................................................................................... 24
Figure 2.8 Stack............................................................................................................................ 25
Figure 2.9 General Register Data Formats (1).............................................................................. 28
Figure 2.9 General Register Data Formats (2).............................................................................. 29
Figure 2.10 Memory Data Formats............................................................................................... 30
Figure 2.11 Instruction Formats (Examples) ................................................................................ 42
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................... 46
Figure 2.13 State Transitions ........................................................................................................ 50
Section 3 MCU Operating Modes
Figure 3.1 H8S/2168 Address Map .............................................................................................. 60
Figure 3.2 H8S/2167 Address Map .............................................................................................. 61
Figure 3.3 H8S/2166 Address Map .............................................................................................. 62
Section 4 Exception Handling
Figure 4.1 Reset Sequence............................................................................................................ 67
Figure 4.2 Stack Status after Exception Handling ........................................................................ 69
Figure 4.3 Operation when SP Value Is Odd................................................................................ 70
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 72
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 .............................................................. 82
Figure 5.3 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE8
(Example of KIN15 to KIN0) ...................................................................................... 83
Figure 5.4 Block Diagram of Interrupt Control Operation ........................................................... 88
Figure 5.5 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0....... 91
Figure 5.6 State Transition in Interrupt Control Mode 1 .............................................................. 92
Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 94
Figure 5.8 Interrupt Exception Handling ...................................................................................... 95
Figure 5.9 Interrupt Control for DTC ........................................................................................... 97
Figure 5.10 Conflict between Interrupt Generation and Disabling............................................... 99
Rev. 3.00, 03/04, page xxv of xl