HD64F2168 Datasheet, PDF (576/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.3.10 SERIRQ Control Register 0 (SIRQCR0)
The SIRQCR0 register contains status bits that indicate the SERIRQ operating mode and status
bits that specify SERIRQ0 interrupt sources.
The SIRQCR0 register is initialized to H'00 by a reset or in hardware standby mode.
R/W
Bit Bit Name Initial Value Slave Host Description
7 Q/C
0
R
 Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
• LPC hardware reset, LPC software reset
• Specification by the stop frame of the SERIRQ
transfer cycle
1: Quiet mode
[Setting condition]
• Specification by the stop frame of the SERIRQ
transfer cycle
6 SELREQ 0
R/W  Start Frame Initiation Request Select
Specifies the condition of start frame activation when
the host interrupt request is cleared in quiet mode.
0: When all host interrupt requests are cleared in
quiet mode, start frame initiation is requested
1: When at least one host interrupt request is
cleared in quiet mode, start frame initiation is
requested
5 IEDIR 0
R/W  Interrupt Enable Direct Mode
Specifies whether LPC channel 2 SERIRQ interrupt
source (SMI, HIRQ6, HIRQ9 to HIRQ11) generation
is conditional upon OBF, or is controlled only by the
host interrupt enable bit.
0: Host interrupt is requested when host interrupt
enable bit and corresponding OBF are both set to
1
1: Host interrupt is requested when host interrupt
enable bit is set to 1
Rev. 3.00, 03/04, page 536 of 830