HD64F2168 Datasheet, PDF (621/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.4.7 LPC Interface Serialized Interrupt Operation (SERIRQ)
A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a supporting function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
16.10.
LCLK
SERIRQ
Drive source
SL
or
Start frame
IRQ0 frame IRQ1 frame IRQ2 frame
H
H
RT SRT SRT SRT
START
IRQ1 Host controller
None
IRQ1
None
LCLK
IRQ14 frame IRQ15 frame IOCHCK frame
SRT SRT SRT I
SERIRQ
Drive source
None
IRQ15
None
Stop frame
H
RT
STOP
Host controller
Next cycle
START
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample, I = Idle
Figure 16.10 SERIRQ Timing
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
Rev. 3.00, 03/04, page 581 of 830