HD64F2168 Datasheet, PDF (503/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.3.9 I²C SMBus Control Register (ICSMBCR)
ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support
the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to
1000 ns. Table 15.6 shows the relationship between the ICSMBCR setting and output data hold
time.
When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled
to access when bit MSTP4 is cleared to 0.
Initial
Bit Bit Name Value R/W Description
7
SMB5E All 0 R/W SMBus Enable
6
SMB4E
5
SMB3E
4
SMB2E
3
SMB1E
2
SMB0E
These bits enable/disable to support the SMBus,
combining with bits FSEL1 and FSEL0. The SMB5E bit
controls IIC_5, the SMB4E bit controls IIC_4, the SMB3E
bit controls IIC_3, the SMB2E bit controls IIC_2, the
SMB1E bit controls IIC_1, the SMB0E bit controls IIC_0.
0: Disables to support the SMBus
1: Enables to support the SMBus
1
FSEL1 0
0
FSEL0 0
R/W Frequency Selection
R/W _{These bits must be specified to match the system clock}
frequency in order to support the SMBus. For details of the
setting, see table 15.7.
Rev. 3.00, 03/04, page 463 of 830