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| HD64F2168 Datasheet, PDF (180/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer | |||
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(4) 16-Bit, 3-State Data Access Space: Figures 6.22 to 6.24 show bus timings for a 16-bit, 3-state
access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states
can be inserted.
Ï
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
Read Cycle
Address
Data
T1 TAW T2
T3
T4 TDSW T5
Write Cycle
Address
Data
T1 TAW T2
T3
T4 TDSW T5
Address
Address
Data
Address
Data
Address
Figure 6.22 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access)
Ï
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
Read Cycle
Address
Data
T1 TAW T2
T3
T4 TDSW T5
Write Cycle
Address
Data
T1 TAW T2
T3
T4 TDSW T5
Address
Address
Address
Data
Address
Data
Figure 6.23 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access)
Rev. 3.00, 03/04, page 140 of 830
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