HD64F2168 Datasheet, PDF (185/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

6.6 Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by the BRSTRM
bit in BCR, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four
or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected
for burst ROM access.
6.6.1 Basic Operation Timing
The number of access states in the initial cycle (full access) of the burst ROM interface is
determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1
or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR.
Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is
performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight
words is performed when the BRSTS0 bit in BCR is set to 1.
The basic access timing for the burst ROM space is shown in figures 6.27 and 6.28.
Full access
Burst access
T₁
T₂
T₃
T₁
T₂
T₁
T₂
φ
Address bus
Only lower address changes
AS/IOS
(IOSE = 0)
RD
Data bus
Read data
Read data
Read data
Figure 6.27 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)
Rev. 3.00, 03/04, page 145 of 830