HD64F2168 Datasheet, PDF (409/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clock synchronous mode, and smart card interface mode. The initial value of BRR is H′FF, and it
can be read from or written to by the CPU at all times.
Table 14.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous mode
Bit Rate
φ × 10⁶
B=
64 × 2 ^{2n – 1}× (N + 1)
Error
φ × 10⁶
Error (%) = {
– 1 } × 100
B × 64 × 2 ^{2n – 1}× (N + 1)
Clock synchronous mode
φ × 10⁶

B=
8 × 2^{2n – 1}× (N + 1)
Smart card interface mode
φ × 10⁶
B=
S × 2 ^{2n + 1}× (N + 1)
φ × 10⁶
Error (%) =
{
B × S × 2 ^{2n + 1}× (N + 1)
–1 } × 100
[Legend]
B:
N:
φ:
n and S:
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following table.
SMR Setting
CKS1
CKS0
n
0
0
0
0
1
1
1
0
2
1
1
3
SMR Setting
BCP1
BCP0
S
0
0
32
0
1
64
1
0
372
1
1
256
Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the
maximum bit rate settable for each frequency. Table 14.6 and 14.8 show sample N settings in
BRR in clock synchronous mode and smart card interface mode, respectively. In smart card
interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
For details, see section 14.7.4, Receive Data Sampling Timing and Reception Margin. Tables 14.5
and 14.7 show the maximum bit rates with external clock input.
Rev. 3.00, 03/04, page 369 of 830