HD64F2168 Datasheet, PDF (145/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

6.3 Register Descriptions
The following registers are provided for the bus controller. For the system control register
(SYSCR), see section 3.2.2, System Control Register (SYSCR). For system control register 2
(SYSCR2), see section 8.6.4, System Control Register 2 (SYSCR2).
• Bus control register (BCR)
• Bus control register 2 (BCR2)
• Wait state control register (WSCR)
• Wait state control register 2 (WSCR2)
6.3.1 Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space and the I/O area range when
the AS/IOS pin is specified as an I/O strobe pin.
Initial
Bit Bit Name Value R/W Description
7
1
R/W Reserved
The initial value should not be changed.
6 ICIS
1
R/W Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle cycle
between successive external read and external write cycles.
0: Idle cycle not inserted
1: 1-state idle cycle inserted
5 BRSTRM 0
R/W Valid only in the normal extended mode.
Burst ROM Enable
Selects the bus interface for the external address space.
0: Basic bus interface
1: Burst ROM interface
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, burst ROM interface cannot be selected for the
256 -kbyte extended area and CP extended area.
4 BRSTS1 1
R/W Valid only in the normal extended mode.
Burst Cycle Select 1
Selects the number of states in the burst cycle of the burst
ROM interface.
0: 1 state
1: 2 states
Rev. 3.00, 03/04, page 105 of 830