HD64F2168 Datasheet, PDF (530/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL
7
8
1
2
3
4
SDA
7
8
1
2
3
4
IRIC
User processing
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
7
8
1
SDA
7
8
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Clear IRIC
Figure 15.27 IRIC Setting Timing and SCL Control (3)
15.4.8 Operation Using the DTC
This LSI provides the DTC to allow continuous data transfer. IIC_4 and IIC_5 cannot use the
DTC. The DTC is initiated when the IRTR flag is set to 1, which is one of the two interrupt flags
(IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of
data transmission regardless of the acknowledge bit value. When the ACKE bit is 1, the ICDRE,
IRIC, and IRTR flags are set if data transmission is completed with the acknowledge bit value of
0, and when the ACKE bit is 1, only the IRIC flag is set if data transmission is completed with the
acknowledge bit value of 1.
When initiated, DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags
to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data
transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, DTC is
not initiated, thus allowing an interrupt to be generated if enabled.
Rev. 3.00, 03/04, page 490 of 830