HD64F2168 Datasheet, PDF (494/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

MST
0
TRS
0
BBSY
1
ESTP
0
STOP
0
IRTR

AASX AL


AAS

ADZ

ACKB

ICDRF
1
0
0
1
0
0


0↓
0↓
0↓

0↓
0
0
1
0
0
1↑/0 
0
0
0

1↑
*²
0

0↓
1↑/0 0/1↑ 






*³
*³
[Legend]
0: 0-state retained 1: 1-state retained : Previous state retained
0↓: Cleared to 0 1↑: Set to 1
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
ICDRE



0↓
State
Reception
end with
ICDRF=1
ICDR read
with the
above state
Automatic
data transfer
from ICDRS
to ICDRR
with the
above state
Stop
condition
detected
Rev. 3.00, 03/04, page 454 of 830