HD64F2168 Datasheet, PDF (582/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
3 IRQ11E2 0
R/W  Host IRQ11 Interrupt Enable 2
Enables or disables a HIRQ11 interrupt request
when OBF2 is set by an ODR2 write.
0: HIRQ11 interrupt request by OBF2 and IRQ11E2
is disabled
[Clearing conditions]
• Writing 0 to IRQ11E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
HIRQ11 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
HIRQ11 interrupt is requested.
[Setting condition]
• Writing 1 after reading IRQ11E2 = 0
2 IRQ10E2 0
R/W  Host IRQ10 Interrupt Enable 2
Enables or disables a HIRQ10 interrupt request
when OBF2 is set by an ODR2 write.
0: HIRQ10 interrupt request by OBF2 and IRQ10E2
is disabled
[Clearing conditions]
• Writing 0 to IRQ10E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
HIRQ10 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
HIRQ10 interrupt is requested.
[Setting condition]
• Writing 1 after reading IRQ10E2 = 0
Rev. 3.00, 03/04, page 542 of 830