HD64F2168 Datasheet, PDF (537/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

t_BUFO fails to meet the I²C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I²C bus.
t_SCLLO in high-speed mode and t_STASO in standard mode fail to satisfy the I²C bus interface
specifications for worst-case calculations of t_Sr/t_Sf. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I²C bus.
Rev. 3.00, 03/04, page 497 of 830