HD64F2168 Datasheet, PDF (495/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.3.7 I²C Bus Status Register (ICSR)
ICSR consists of status flags. Also see tables 15.4 and 15.5.
Initial
Bit
Bit Name Value R/W Description
7
ESTP
0
R/(W)* Error Stop Condition Detection Flag
This bit is valid in I²C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame transfer.
[Clearing conditions]
• When 0 is written in ESTP after reading ESTP = 1
• When the IRIC flag in ICCR is cleared to 0
6
STOP
0
R/(W)* Normal Stop Condition Detection Flag
This bit is valid in I²C bus format slave mode.
[Setting condition]
When a stop condition is detected after frame transfer is
completed.
[Clearing conditions]
• When 0 is written in STOP after reading STOP = 1
5
IRTR
0
• When the IRIC flag is cleared to 0
R/(W)* I²C Bus Interface Continuous Transfer Interrupt Request
Flag
Indicates that the I²C bus interface has issued an interrupt
request to the CPU, and the source is completion of
reception/transmission of one frame in continuous
transmission/reception for which DTC activation is
possible. When the IRTR flag is set to 1, the IRIC flag is
also set to 1 at the same time.
[Setting conditions]
I²C bus format slave mode:
• When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
I²C bus format master mode or clocked synchronous serial
format mode:
• When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
• When 0 is written after reading IRTR = 1
• When the IRIC flag is cleared to 0 while ICE is 1
Rev. 3.00, 03/04, page 455 of 830