HD64F2168 Datasheet, PDF (566/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.3.5 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H,
LADR1L, LADR2H, and LADR2L.
When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L)
are set through LADR12. The contents of the address field in LADR1 must not be changed while
channel 1 is operating (while LPC1E is set to 1).
When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set
through LADR12. The contents of the address field in LADR2 must not be changed while channel
2 is operating (while LPC2E is set to 1).
Table 16.2 shows the initial value of each register. Table 16.3 shows the host register selection in
address match determination. Table 16.4 shows the slave selection internal registers in slave (this
LSI) access.
Table 16.2 LADR1, LADR2 Initial Values
Register Name
LADR1
LADR2
Initial Value
H'0060
H'0062
Description
I/O address of channel 1
I/O address of channel 2
Table 16.3 Host Register Selection
Bits 15 to 3
I/O Address
Bit 2 Bit 1
Bit 0
Transfer
Cycle Host Register Selection
LADR1 (bits 15 to 3) 0
LADR1 (bit 1) LADR1 (bit 0) I/O write IDR1 write (data),
C/D1 ← 0
LADR1 (bits 15 to 3) 1
LADR1 (bit 1) LADR1 (bit 0) I/O write IDR1 write (command),
C/D1 ← 1
LADR1 (bits 15 to 3) 0
LADR1 (bit 1) LADR1 (bit 0) I/O read ORD1 read
LADR1 (bits 15 to 3) 1
LADR1 (bit 1) LADR1 (bit 0) I/O read STR1 read
LADR2 (bits 15 to 3) 0
LADR2 (bit 1) LADR2 (bit 0) I/O write IDR2 write (data),
C/D2 ← 0
LADR2 (bits 15 to 3) 1
LADR2 (bit 1) LADR2 (bit 0) I/O write IDR2 write (command),
C/D2 ← 1
LADR2 (bits 15 to 3) 0
LADR2 (bit 1) LADR2 (bit 0) I/O read ODR2 read
LADR2 (bits 15 to 3) 1
LADR2 (bit 1) LADR2 (bit 0) I/O read STR2 read
Rev. 3.00, 03/04, page 526 of 830