HD64F2168 Datasheet, PDF (360/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

12.3.9 Timer Input Select Register (TISR)
TISR selects a signal source of external clock/reset input for the counter.
Bit
7 to 1
0
Bit Name Initial Value R/W

All 1
R/W
IS
0
R/W
Description
Reserved
The initial values should not be modified.
Input Select
Selects TMIY or ExTMIY as the signal source of
external clock/reset input for the TMR_Y counter.
When external reset input is selected for the CCLR0
and CCLR1 in TCR_Y or external clock is selected
for the CKS2 to CKS0 in TCR_Y, set this bit to1.
0: TMIY or ExTMIY (TMCIY/TMRIY) is not selected
1: TMIY or ExTMIY (TMCIY/TMRIY) is selected
12.3.10 Timer Connection Register I (TCONRI)
TCONRI controls TMR_X input capture.
Bit
7 to 5
4
3 to 0
Bit Name

ICST

Initial Value R/W
All 0
R/W
0
R/W
All 0
R/W
Description
Reserved
The initial values should not be modified.
Input Capture Start Bit
TMR_X has input capture registers (TICR,
TICRR, and TICRF). TICRR and TICRF can
measure the width of a pulse by means of a
single capture operation under the control of the
ICST bit. When a rising edge followed by a falling
edge is detected on TMRIX after the ICST bit is
set to 1, the contents of TCNT at those points are
captured into TICRR and TICRF, respectively,
and the ICST bit is cleared to 0.
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIX
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Reserved
The initial values should not be modified.
Rev. 3.00, 03/04, page 320 of 830