HD64F2168 Datasheet, PDF (286/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

• PE0/LAD0
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE0DDR.
LPC
PE0DDR
Pin Function
0
PE0 input pin
Disabled
1
PE0 output pin
Enabled

LAD0 input/output pin
8.15 Port F
Port F is a 3-bit multi-function input/output port supporting the following register set.
• Port F data direction register (PFDDR)
• Port F output data register (PFODR)
• Port F input data register (PFPIN)
8.15.1 Port F Data Direction Register (PFDDR)
PFDDR is used to specify the input/output attribute of each pin of port F.
Bit
7 to 3
2
1
0
Bit Name

PF2DDR
PF1DDR
PF0DDR
Initial Value

0
0
0
R/W Description
 Reserved
W When the given bit of PFDDR is set to 1, the
W ^{corresponding pin of port F will function as an output}
port, and when the bit is cleared to 0, the port pin will
W _{function as an input port.}
This register is assigned to the same address as that
of PFPIN. When this address is read, the port F states
are returned.
8.15.2 Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins.
Bit
7 to 3
2
1
0
Bit Name Initial Value


PF2ODR 0
PF1ODR 0
PF0ODR 0
R/W Description
 Reserved. When this bit is read, an undefined value is
returned.
R/W The PFODR register stores the output data for the
R/W ^{pins that are used a general output port.}
R/W
Rev. 3.00, 03/04, page 246 of 830