HD64F2168 Datasheet, PDF (492/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 15.4 Flags and Transfer States (Master Mode)
MST TRS BBSY ESTP STOP IRTR
1
1
0
0
0
0
AASX AL
0↓
0
AAS
0↓
ADZ
0↓
ACKB
0
1
1
1↑ 0
0
1↑ 0
0
0
0
0
1

1
0
0

0
0
0
0

1
1
1
0
0

0
0
0
0
1↑
1
1
1
0
0
1↑ 0
0
0
0
0
1
1
1
0
0

0
0
0
0
0
1
1
1
0
0

0
0
0
0
0
1
1
1
0
0

0
0
0
0
0
1
1
1
0
0
1↑ 0
0
0
0
0
1
0
1
0
0
1↑ 0
0
0
0

1
0
1
0
0

0
0
0
0

1
0
1
0
0

0
0
0
0

1
0
1
0
0

0
0
0
0

1
0
1
0
0
1↑ 0
0
0
0

0↓ 0↓ 1
0
0

0
1↑ 0
0

1

0↓ 0
0

0
0
0
0

[Legend]
0: 0-state retained
0↓: Cleared to 0
1: 1-state retained
1↑: Set to 1
: Previous state retained
ICDRF









1↑
0↓
1
0↓
1↑


ICDRE
0
1↑


1↑
0↓
1
0↓
1↑






0↓
State
Idle state (flag
clearing
required)
Start condition
detected
Wait state
Transmission
end (ACKE=1
and ACKB=1)
Transmission
end with
ICDRE=0
ICDR write with
the above state
Transmission
end with
ICDRE=1
ICDR write with
the above state
or after start
condition
detected
Automatic data
transfer from
ICDRT to ICDRS
with the above
state
Reception end
with ICDRF=0
ICDR read with
the above state
Reception end
with ICDRF=1
ICDR read with
the above state
Automatic data
transfer from
ICDRS to
ICDRR with the
above state
Arbitration lost
Stop condition
detected
Rev. 3.00, 03/04, page 452 of 830