HD64F2168 Datasheet, PDF (601/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
4 BEVT_ATN 0
R/(W)*¹ R/(W)*⁵ Event Interrupt
Sets when the slave detects an event to the host.
Setting the B2H_IRQ_EN bit in the BTIMSR
register enables the BEVT_ATN bit to be used as
an interrupt source to the host.
3 B2H_ATN 0
0: No event interrupt request is available
[Clearing condition]
When the host writes a 1 to the bit.
1: An event interrupt request is available
[Setting condition]
When the slave writes a 1 after a 0 has been read
from BEVT_ATN.
R/(W)*¹ R/(W)*⁵ Slave Buffer Write End Indication Flag
This status flag indicates that the slave has finished
writing all data to the BTDTR buffer. Setting the
B2H_IRQ_EN bit in the BTIMSR register enables
the B2H_ATN bit to be used as an interrupt source
to the host.
0: Host has completed reading the BTDTR buffer
[Clearing condition]
When the host writes a 1
2 H2B_ATN 0
1: Slave has completed writing to the BTDTR buffer
[Setting condition]
When the slave writes a 1 after a 0 has been read
from B2N_ATN.
R/(W)*² R/(W)*¹ Host Buffer Write End Indication Flag
This status flag indicates that the host has finished
writing all data to the BTDTR buffer.
0: Slave has completed reading the BTDTR buffer
[Clearing condition]
When the slave writes a 0 after a 1 has been read
from H2B_ATN.
1: Host has completed writing to the BTDTR buffer
[Setting condition]
When the host writes a 1
Rev. 3.00, 03/04, page 561 of 830