HD64F2168 Datasheet, PDF (627/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.6 Usage Notes
16.6.1 Module Stop Setting
The LPC operation stop or enable can be specified by the module stop control register. With the
initial value, LPC operation will stop. Releasing module stop mode enables access to the register.
For details see section 23, Power-Down Modes.
16.6.2 Usage Note of LPC Interface
The LPC interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR is required to avoid data
contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the right to access TWR1 to TWR15
has been obtained.
Table 16.13 shows the host address example of registers LADR3, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15.
Rev. 3.00, 03/04, page 587 of 830