HD64F2168 Datasheet, PDF (587/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
3 SEVT_ 0
ATN
R/W R
Event Flag
When the slave detects an event for the host, this bit
is set.
0: Indicates waiting for event detection
1: Indicates event detection
2 SMS_ 0
ATN
R/W R
SMS Flag
When there is a message to be transmitted from the
slave to the host, this bit is set.
0: There is not a message
1: There is a message
1
0
R/W R Reserved
The initial value should not be changed.
0 BUSY 0
R/(W)* W SMIC Busy
This bit indicates that the slave is now transferring
data. This bit can be cleared only by the slave and
set only by the host.
The rising edge of this bit is a source of internal
interrupt to the slave.
0: Transfer cycle wait state
[Clearing conditions]
After the slave reads BUSY = 1, writes 0 to this bit.
1: Transfer cycle in progress
[Setting condition]
When the host writes 1 to this bit.
Note: Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 547 of 830