HD64F2168 Datasheet, PDF (642/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

18.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t_D) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 indicates
the A/D conversion time.
As indicated in figure 18.2, the A/D conversion time (t_CONV) includes t_D and the input sampling time
(t_SPL). The length of t_D varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 18.3.
In scan mode, the values given in table 18.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 266 states (fixed) when CKS = 0 and 134 states
(fixed) when CKS = 1.
Use the conversion time of 134 state only when the system clock (φ) is 16 MHz or lower.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t_D: A/D conversion start delay
t_SPL: Input sampling time
t_CONV: A/D conversion time
t_CONV
Figure 18.2 A/D Conversion Timing
Rev. 3.00, 03/04, page 602 of 830