HD64F2168 Datasheet, PDF (35/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Tables
Section 1 Overview
Table 1.1 Pin Arrangement in Each Operating Mode............................................................... 4
Table 1.2 Pin Functions ............................................................................................................ 9
Section 2 CPU
Table 2.1 Instruction Classification ........................................................................................ 31
Table 2.2 Operation Notation ................................................................................................. 32
Table 2.3 Data Transfer Instructions....................................................................................... 33
Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 34
Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 35
Table 2.5 Logic Operations Instructions................................................................................. 36
Table 2.6 Shift Instructions..................................................................................................... 36
Table 2.7 Bit Manipulation Instructions (1)............................................................................ 37
Table 2.7 Bit Manipulation Instructions (2)............................................................................ 38
Table 2.8 Branch Instructions ................................................................................................. 39
Table 2.9 System Control Instructions.................................................................................... 40
Table 2.10 Block Data Transfer Instructions ............................................................................ 41
Table 2.11 Addressing Modes .................................................................................................. 43
Table 2.12 Absolute Address Access Ranges ........................................................................... 45
Table 2.13 Effective Address Calculation (1)........................................................................... 47
Table 2.13 Effective Address Calculation (2)........................................................................... 48
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection ............................................................................ 53
Table 3.2 Pin Functions in Each Mode ................................................................................... 59
Section 4 Exception Handling
Table 4.1 Exception Types and Priority.................................................................................. 63
Table 4.2 Exception Handling Vector Table........................................................................... 64
Table 4.2 Exception Handling Vector Table (cont) ................................................................ 65
Table 4.3 Status of CCR after Trap Instruction Exception Handling ..................................... 68
Section 5 Interrupt Controller
Table 5.1 Pin Configuration.................................................................................................... 73
Table 5.2 Correspondence between Interrupt Source and ICR ............................................... 75
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 85
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) ...................... 86
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) ...................... 87
Table 5.4 Interrupt Control Modes ......................................................................................... 88
Table 5.5 Interrupts Selected in Each Interrupt Control Mode ............................................... 89
Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode............ 90
Table 5.7 Interrupt Response Times ....................................................................................... 96
Rev. 3.00, 03/04, page xxxv of xl