HD64F2168 Datasheet, PDF (480/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

If IIC is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is
transferred automatically from ICDRS to ICDRR, following reception of one frame of data using
ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically
from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from
ICDRS to ICDRR. Always set IIC to receive mode before reading from ICDR.
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
15.3.2 Slave Address Register (SAR)
SAR sets the slave address and selects the communication format. When the LSI is in slave mode
with the I²C bus format selected, if the FS bit is set to 0 and the upper 7 bits of SAR match the
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to
0.
Initial
Bit Bit Name Value
7 SVA6
All 0
6 SVA5
5 SVA4
4 SVA3
3 SVA2
2 SVA1
1 SVA0
0 FS
0
R/W Description
R/W Slave Address
Set a slave address.
R/W Format Select
Selects the communication format together with the FSX
bit in SARX. Refer to table 15.2.
This bit should be set to 0 when general call address
recognition is performed.
Rev. 3.00, 03/04, page 440 of 830